Évaluations - 3, GPA: 4.3
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Facilité d'utilisation
This signal falls when the subcode are in standby stase. 51 SBCK I Subcode readout clock input. This is a Schmitt input. 52 FSX O Output pin for the 7.35 kHZ synchronization signal divided from the crystal oscillator. 53 WRQ O Subcode Q output standby output. 54 RWC I Read/write control input. This is a Schmitt input. 55 SQOUT O Subcode Q output. 56 COIN I Command input pin from control microprocessor. 57 CQCK I Input for both the command input acquisition clock and the SQOUT pin subcode readout clock input pin. This is Schmitt input. 58 RES I Reset input. This pin must be set low briefly after power is first applied. 59 TST11 O Test output. Leave open. (Normally output a low level.) 60 16M O 16.9344 MHz output. 61 4.2M O 4.2336 MHz output. 62 TEST5 I Test input. A pull-down resistor is built-in. (Must be connected to 0V.) 63 CS I Chip seledt input. A pull-down resistor is built-in. (Must be connected to 0V if not controlled.) 64 TEST1 I Test input. No pull-down resistor. (Must be connected to 0V.) - 28 - IC, LC75374E Pin No. Pin Name I/O Description 1 RVRIN I 4dB volume control input. Must be driven at a low impedance. 2 RCOM - 1dB volume control common pin. 3 ~ 5 RT1 ~ RT3 - For the connection of capacitors that compensate for bass and treble in the tone control circuits. A high-frequency compensation capacitors must be connected between T1 and T2. A low-frequency compensation capacitors must be connected between T2 and T3. 6 RTOUT O Tone control output. 7 RSIN I Super bass input. Must be driven at a low impedance. 8 NC - Connected to VSS. 9 NC - Not used. 10 ~ 11 RSB1 ~ RSB2 - For the connection of RCH super bass compensation capacitors. 12 RFIN I Fader input. Must be driven at a low impedance. 13 RFOUT O Fader outputs. The front and rear sides can be attenuated independently. 14 RROUT 15 VSS - Ground. 16 CL I Serial data and clock inputs for control. 17 DI 18 CE - Chip enable. Data is written in the internal latch when the chip enable signal goes "L" from "H", and each analog switch is activated. Data transfer is enabled at "H". 19 VREF - Generates a 1/2VDD power source. A capacitor must be connected between VREF and VSS as a troubleshooting against power ripples. 20 LROUT O Fader outputs. The frount and rear sides can be attenuated independently. 21 LFOUT 22 LFIN I Fader input. Must be driven at a low impedance. 23 ~ 24 LSB2~LSB1 - For the connection of LCH super bass compensation capacitors. 25 NC - Not used. 26 NC - Connected to VSS. 27 LSIN I Super bass input. Must be driven at a low impedance. 28 LTOUT O Tone control output. 29 ~ 31 LT3 ~ LT1 - For the connection of capacitors that compensate for bass and treble in the tone control circuit. A high-frequency compensation capacitors must be connected between T1 and T2. A low-frequency compensation capacitors must be connected between T2 and T3. 32 LCOM - 1dB volume control common pin. 33 LVRIN I 4dB volume control input. Must be driven at a low impedance. 34 LSELO O Input selector output pin. 35 AUX(L) I Signal input pins. 36 CD(L) 37 TUN(L) 38 TP(L) 39 VDD - Power supply. - 29 - Pin No. Pin Name 40 TP(R) 41 TUN(R) 42 CD(R) 43 AUX(R) 44 RSELO I/O Description Signal input pins. O Input selector output pin. I IC, LC75853NW Pin No. Pin Name I/O Description 1 ~ 40 S1 ~ S40 O LCD segment output. 41 ~ 43 COM1~ COM3 O LCD command driver outputs. 44 ~ 49 KS1 ~ KS6 O Key scan outputs. 50 ~ 54 KI1 ~ KI5 I Key scan inputs. These pins have build-in pull-down resistor. 55 TEST - Test pin. (Connected to GND.) 56 VDD - Power supply. 57 VDD1 I Used for applying the LCD drive 2/3 bias voltage externally. (Must be connected to VDD2 when a 1/2 bias drive scheme is used.) 58 VDD2 I Used for applying the LCD drive 1/3 bias voltage externally. (Must be connected to VDD1 when a 1/2 bias drive scheme is used. 59 VSS - Power supply. (Connected to GND.) 60 OSC I/O Resistor and capacitor are attached externally form an oscillator circuit. 61 DO O Serial data interface pin; output data. 62 CE O Serial data interface pin; chip enable. 63 CL O Serial data interface pin; synchronization. 64 DI O Serial data interface pin; data transferred. - 30 - CD TEST MODE 1 -1 How to Activate CD Test Mode 1) Connect 62 pin (test) of IC701 (LC72358N-9910) on MAIN C.B to the 31 pin (VDD) by cable. 2) Connect wire of ACC (red) and BACKUP (yellow) of power supply/speaker connector to DC+12V, then connect Ground (black) to When CD test mode is started, all displays will be lighted as shown in the following figure. 1-2 How to cancel CD Test Mode 1) Disconnect the cable of 62 pin (test) and 31 pin (VDD) of the MAIN C.B IC701 (LC72358N-9910) and switch on the power. 1-3 CD Test Mode Functions MODE Keys to operate Display Operations Contents Start Mode All lightented •Start TEST MODE Search Mode RANDOM TOC READING • Continual Focus Search (The pickup lens respeats the full-swing up-down motion) * NO...