Fabricant : Texas Instruments
Taille : 2.06 mb
Nom Fichier : TMS320C209-users-guide.pdf
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Facilité d'utilisation
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Copyright W 1996, Texas Instruments Incorporated Preface Read This First About This Manual This user’s guide describes the architecture, hardware, assembly language instructions, and general operation of the TMS320C2xx digital signal processors (DSPs). This manual can also be used as a reference guide for developing hardware and/or software applications. In this document, ’C2xx refers to any of the TMS320C2xx devices, except where device-specific information is explicitly stated. When device-specific information is given, the device name may be abbreviated; for example, TMS320C203 will be abbreviated as ’C203. How to Use This Manual Chapter 1, Introduction, summarizes the TMS320 family of products and then introduces the key features of the TMS320C2xx generation of that family. Chapter 2, Architectural Overview, summarizes the ’C2xx architecture, providing information about the CPU, bus structure, memory, on-chip peripherals, and scanning logic. If you are reading this manual to learn about the ’C209, Chapter 11 is important for you. There are some notable differences between the ’C209 and other ’C2xx devices, and Chapter 11 explains these differences. In addition, it shows how to use this manual to get a complete picture of the ’C209. The following table points you to major topics. How to Use This Manual For this information: Look here: Addressing modes (for addressing data Chapter 6, Addressing Modes memory) Assembly language instructions Chapter 7, Assembly Language Instructions Assembly language instructions of Appendix B, TMS320C1x, ’C2x, ’C2xx, and ’C5x TMS320C1x/C2x/C2xx/C5x compared Instruction Set Comparison Boot loader Chapter 4, Memory and I/O Spaces Clock generator Chapter 8, On-Chip Peripherals CPU Chapter 3, Central Processing Unit Custom ROM from TI Appendix D, Submitting ROM Codes to TI Emulator Appendix E, Design Considerations for Using XDS510 Emulator Features Chapter 1, Introduction Chapter 2, Architectural Overview Input/output ports Chapter 4, Memory and I/O Spaces Interrupts Chapter 5, Program Control Memory configuration Chapter 4, Memory and I/O Spaces Memory interfacing Chapter 4, Memory and I/O Spaces On-chip peripherals Chapter 8, On-Chip Peripherals Pipeline Chapter 5, Program Control Program control Chapter 5, Program Control Program examples Appendix C, Program Examples Program-memory address generation Chapter 5, Program Control Registers summarized Appendix A, Register Summary Serial ports Chapter 9, Synchronous Serial Port Chapter 10, Asynchronous Serial Port Stack Chapter 5, Program Control Status registers Chapter 5, Program Control Timer Chapter 8, On-Chip Peripherals TMS320C209 differences and Chapter 11, TMS320C209 similarities Wait-state generator Chapter 8, On-Chip Peripherals Notational Conventions/Information About Cautions Notational Conventions This document uses the following conventions: . Program listings and program examples are shown in a special typeface. Here is a segment of a program listing: OUTPUT LDP #6 ;select data page 6 BLDD #300, 20h ;move data at address 300h to 320h RET . In syntax descriptions, bold portions of a syntax should be entered as shown;italic portions of a syntax identify information that you specify. Here is an example...