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Fabricant : AMD Taille : 3.36 mb Nom Fichier : 33234H_LX_databook.pdf Langue d'enseignement:

VGA Block Configuration Register Summary DC Memory Offset Type Register Name Reset Value Reference 100h R/W VGA Configuration (VGA_CONFIG) 00000000h Page 355 104h RO VGA Status (VGA_STATUS) 00000000h Page 355 Table 6-49. VGA Block Standard Register Summary I/O Read Address I/O Write Address Register Name/Group Reset Value Reference 3CCh 3C2h (W) VGA Miscellaneous Output 02h Page 356 3C2h -VGA Input Status Register 0 00h Page 357 3BAh or 3DAh (Note 1) -VGA Input Status Register 1 01h Page 357 3CAh 3BAh or 3DAh (Note 1) VGA Feature Control xxh Page 357 3C4h VGA Sequencer Index 0xh Page 358 3C5h VGA Sequencer Data xxh Page 358 3B4h or 3D4h (Note 1) CRTC Index 00h Page 362 3B5h or 3D5h (Note 1) CRTC Data 00h Page 363 3CEh VGA Graphics Controller Index xxh Page 373 3CFh VGA Graphics Controller Data xxh Page 374 3C0h Attribute Controller Index/Data xxh Page 379 3C1h (R) 3C0h (W) 3C8h 3C7h (Palette Read Mode) Video DAC Palette Address 00h Page 382 3C8h (Palette Write Mode) 3C7h-Video DAC State 00h Page 383 3C9h Video DAC Palette Data 00h Page 383 3C6h Video DAC Palette Mask 00h Page 384 Note 1. The I/O addresses are determined by bit 0 of the Miscellaneous Output Register. See the description of this register in Section 6.6.17.1 on page 356 for more information. AMD Geode™ LX Processors Data Book 33234H Display Controller Register Descriptions Table 6-50. VGA Block Extended Register Summary VGA CRTC Index Type Register Name Reset Value Reference 0030h R/W ExtendedRegisterLock FFh Page 385 043h R/W ExtendedModeControl 00h Page 385 044h R/W ExtendedStartAddress 00h Page 385 047h R/W WriteMemoryAperture 00h Page 386 048h R/W ReadMemoryAperture 00h Page 386 060h R/W BlinkCounterCtl 00h Page 386 061h RO BlinkCounter 00h Page 387 070h R/W VGALatchSavRes 00h Page 387 071h R/W DACIFSavRes 00h Page 387 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions 33234H 6.6.1 Standard GeodeLink™ Device (GLD) Registers (MSRs) 6.6.1.1 GLD Capabilities MSR (GLD_MSR_CAP) MSR Address 80002000h Type RO Reset Value 00000000_0003E4xxh GLD_MSR_CAP Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD DEV_ID REV_ID GLD_MSR_CAP Bit Descriptions Bit Name Description 63:24 RSVD Reserved. Set to 0. 23:8 DEV_ID Device ID. Identifies device (03E4h). 7:0 REV_ID Revision ID. Identifies device revision. See AMD Geode™ LX Processors Specification Update document for value. 6.6.1.2 GLD Master Configuration MSR (GLD_MSR_CONFIG) MSR Address 80002001h Type R/W Reset Value 00000000_00000000h GLD_MSR_CONFIG Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD PRI1 RSVDPRI0 RSVDPID GLD_MSR_CONFIG Bit Descriptions Bit Name Description 63:11 RSVD Reserved. Set to 0. 10:8 PRI1 Secondary Priority Level. This value is the priority level the DC uses when performing high priority GLIU0 accesses. This is the case when the FIFOs are nearly empty. 7 RSVD Reserved. Set to 0. 6:4 PRI0 Primary Priority Level. This value is the priority level the DC uses for most accesses (i.e., when the display FIFO is not in danger of being emptied). 3 RSVD Reserved. Set to 0. 2:0 PID Priority ID. This value is the Priority ID (PID) value used when the DC initiates GLIU0 transactions. AMD Geode™ LX Processors Data Book 33234H Display Controller Register Descriptions 6.6.1.3 GLIU0 Device SMI MSR (GLD_MSR_SMI) MSR Address 80002002h Type R/W Reset Value 00000000_00000000h GLD_MSR_SMI Register Map 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RSVD VGA_RES_CHANGE_SMIRSVD ISR1R_SMIMISCIOR_SMIDACIOR_ SMIDACIOW_ SMIATRIOR_ SMIATRIOW_ SMIGFXIOR_SMIGFXIOW_SMISEQIOR_SMISEQIOW_SMICRTCIOR_ SMICRTCIOW_SMICRTCIO_SMIVGA_ BL_ SMIISR0_SMIMISC_SMIVG_BL_SMI 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD VGA_RES_CHANGE_MASKRSVD ISR1R_MSKMISCIOR_ MSKDACIOR_ MSKDACIOW_ MSKATRIOR_ MSKATRIOW_ MSKGFXIOR_MSKGFXIOW_MSKSEQIOR_MSKSEQIOW_ MSKCRTCIOR_MSKCRTCIOW_ MSKCRTCIO_MSKVGA_BL_MSKISR0_MSKMISC_MSKVG_BL_MSK GLD_MSR_SMI Bit Descriptions Bit Name Description 63:61 RSVD Reserved. Set to 0. 60 VGA_RES_ CHANGE_SMI VGA Resolution Change SMI. Reading a 1 indicates that the VGA’s output image size has changed while scaling is enabled. The handler for this SMI should update the horizontal and/or vertical scale factor(s) accordingly. 59:49 RSVD Reserved. Set to 0. 48 ISR1R_SMI Input Status Register 1 Read SMI. Reading a 1 indicates that the VGA Input Status Register 1 has been read; writing this bit to 1 clears it. 47 MISCIOR_SMI Miscellaneous Output Register Read SMI. Reading a 1 indicates that the VGA Miscellaneous Output Register has been read; writing this bit to 1 clears it. 46 DACIOR_SMI Video DAC Register ...

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