Évaluations - 5, GPA: 3.6
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A wait is generated. 6) The cycle completes after IDE_IORDY[0:1] is reasserted. For cycles where a wait is generated and IDE_IOR[0:1] is asserted, the device places read data on IDE_DATA[15:0] for tRD before asserting IDE_IORDY[0:1]. Figure 9-24. Register Transfer to/from Device Timing Diagram AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B Table 9-26. IDE PIO Data Transfer to/from Device Timing Parameters Symbol Parameter Mode Unit Comments0 1 2 3 4 t0 Cycle time (min) 600 383 240 180 120 ns Note 1 t1 Address valid to IDE_IOR[0:1]#/ IDE_IOW[0:1]# setup (min) 70 50 30 30 25 ns t2 IDE_IOR[0:1]#/IDE_IOW[0:1]# 16-bit (min) 165 125 100 80 70 ns Note 1 t2i IDE_IOR[0:1]#/IDE_IOW[0:1]# recovery time (min) ---70 25 ns Note 1 t3 IDE_IOW[0:1]# data setup (min) 60 45 30 30 20 ns t4 IDE_IOW[0:1]# data hold (min) 30 20 15 10 10 ns t5 IDE_IOR[0:1]# data setup (min) 50 35 20 20 20 ns t6 IDE_IOR[0:1]# data hold (min) 5 5 5 5 5 ns t6Z IDE_IOR[0:1]# data TRI-STATE (max) 30 30 30 30 30 ns Note 2 t9 IDE_IOR[0:1]#/IDE_IOW[0:1]# to address valid hold (min) 20 15 10 10 10 ns tRD Read Data Valid to IDE_IORDY[0,1] active (if IDE_IORDY[0:1] initially low after tA) (min) 0 0 0 0 0 ns tA IDE_IORDY[0:1] Setup time 35 35 35 35 35 ns Note 3 tB IDE_IORDY[0:1] Pulse Width (max) 1250 1250 1250 1250 1250 ns tC IDE_IORDY[0:1] assertion to release (max) 5 5 5 5 5 ns Note 1. t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the command active time and the command inactive time. The three timing requirements of t0, t2, and t2i are met. The minimum total cycle time requirement is greater than the sum of t2 and t2i. (This means that a host implementation may lengthen t2 and/or t2i to ensure that t0 is equal to or greater than the value reported in the device’s IDENTIFY DEVICE data.) Note 2. This parameter specifies the time from the rising edge of IDE_IOR[0:1]# to the time that the data bus is no longer driven by the device (TRI-STATE). Note 3. The delay from the activation of IDE_IOR[0:1]# or IDE_IOW[0:1]# until the state of IDE_IORDY[0:1] is first sampled. If IDE_IORDY[0:1] is inactive, then the host waits until IDE_IORDY[0:1] is active before the PIO cycle is completed. If the device is not driving IDE_IORDY[0:1] negated after the activation (tA) of IDE_IOR[0:1]# or IDE_IOW[0:1]#, then t5 is met and tRD is not applicable. If the device is driving IDE_IORDY[0:1] negated after the activation (tA) of IDE_IOR[0:1]# or IDE_IOW[0:1]#, then tRD is met and t5 is not applicable. AMD Geode™ SC2200 Processor Data Book 32580B Electrical Specifications t0 ADDR valid1 t9 t1 t2 t2i IDE_IOR0# IDE_IOW0# WRITE IDE_DATA[15:0] t3 t4 READ IDE_DATA[15:0] t5 t6 IDE_IORDY02,3 t6z tA tC tRD IDE_IORDY02,4 IDE_IORDY02,5 tB tC Notes: 1) Device address consists of signals IDE_CS[0:1]# and IDE_ADDR[2:0]. 2) Negation of IDE_IORDY[0:1] is used to extend the PIO cycle. The determination of whether or not the cycle is to be extended is made by the host after tA from the assertion of IDE_IOR[0:1]# or IDE_IOW[0:1]#. 3) Device never negates IDE_IORDY[0:1]. Devices keep IDE_IORDY[0:1] released, and no wait is generated. 4) Device negates IDE_IORDY[0:1] before tA but causes IDE_IORDY[0:1] to be asserted before tA. IDE_IORDY[0:1] is released, and no wait is generated. 5) Device negates IDE_IORDY[0:1] before tA. IDE_IORDY[0:1] is released prior to negation and may be asserted for no more than 5 ns before release. A wait is generated. 6) The cycle completes after IDE_IORDY[0:1] is reasserted. For cycles where a wait is generated and IDE_IOR[0:1]# is asserted, the device places read data on IDE_DATA[15:0] for tRD before asserting IDE_IORDY[0:1]. Figure 9-25. PIO Data Transfer to/from Device Timing Diagram AMD Geode™ SC2200 Processor Data Book Electrical Specifications 32580B Table 9-27. IDE Multiword DMA Data Transfer Timing Parameters Symbol Parameter Mode Unit Comments0 1 2 t0 Cycle time (min) 480 150 120 ns Note 1 tD IDE_IOR[0:1]#/IDE_IOW[0:1]# (min) 215 80 70 ns tE IDE_IOR[0:1]# data access (max) 150 60 50 ns tF IDE_IOR[0:1]# data hold (min) 5 5 5 ns tG IDE_IOW[0:1]#/IDE_IOW[0:1]# data setup (min) 100 30 20 ns tH IDE_IOW[0:1]# data hold (min) 20 15 10 ns tI IDE_DACK[0:1]# to IDE_IOR[0:1]#/ IDE_IOW[0:1]# setup (min) 0 0 0 ns tJ IDE_IOR[0:1]#/IDE_IOW[0:1]# to IDE_DACK[0:1]# hold (min) 20 5 5 ns tKR IDE_IOR[0:1]# negated pulse width (min) 50 50 25 ns tKW IDE_IOW[0:1]# negated pulse width (min) 215 50 25 ns tLR IDE_IOR[0:1]# to IDE_DREQ[0:1] delay (max) 120 40 35 ns tLW IDE_IOW[0:1]# to IDE_DREQ0,1 delay (max) 40 40 35 ns tM IDE_CS[0:1]# valid to IDE_IOR[0:1]#/ IDE_IOW[0:1]# (min) 50 30 25 ns tN IDE_CS[0:1]# hold 15 10 10 ns tZ IDE_DACK[0:1]# to TRI-STATE 20 25 25 ns Note 1. t0 is the minimum total cycle time, tD is the minimum command active time, and tKR or tKW is the minimum command recovery time or command inactive time. The a...