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Error Messages and Beep Codes 4.5 Port 80h POST Codes During the POST, the BIOS generates diagnostic progress codes (POST codes) to I/O port 80h. If the POST fails, execution stops and the last POST code generated is left at port 80h. This code is useful for determining the point where an error occurred. Displaying the POST codes requires a PCI bus add-in card, often called a POST card. The POST card can decode the port and display the contents on a medium such as a seven-segment display. NOTE The POST card must be installed in the PCI bus connector. The following tables provide information about the POST codes generated by the BIOS: • Table 40 lists the Port 80h POST code ranges • Table 41 lists the Port 80h POST codes themselves • Table 42 lists the Port 80h POST sequence NOTE In the tables listed above, all POST codes and range values are listed in hexadecimal. Table 40. Port 80h POST Code Ranges Range Category/Subsystem 00 – 0F Debug codes: Can be used by any PEIM/driver for debug. 10 – 1F Host Processors: 1F is an unrecoverable CPU error. 20 – 2F Memory/Chipset: 2F is no memory detected or no useful memory detected. 30 – 3F Recovery: 3F indicated recovery failure. 40 – 4F Reserved for future use. 50 – 5F I/O Busses: PCI, USB, ATA, etc. 5F is an unrecoverable error. Start with PCI. 60 – 6F Reserved for future use (for new busses). 70 – 7F Output Devices: All output consoles. 7F is an unrecoverable error. 80 – 8F Reserved for future use (new output console codes). 90 – 9F Input devices: Keyboard/Mouse. 9F is an unrecoverable error. A0 – AF Reserved for future use (new input console codes). B0 – BF Boot Devices: Includes fixed media and removable media. BF is an unrecoverable error. C0 – CF Reserved for future use. D0 – DF Boot device selection. E0 – FF E0 – EE: Miscellaneous codes. See Table 41. EF: boot/S3 resume failure. F0 – FF: FF processor exception. Intel Desktop Board DH55TC Technical Product Specification Table 41. Port 80h POST Codes POST Code Description of POST Operation Host Processor 10 Power-on initialization of the host processor (Boot Strap Processor) 11 Host processor cache initialization (including APs) 12 Starting Application processor initialization 13 SMM initialization Chipset 21 Initializing a chipset component Memory 22 Reading SPD from memory DIMMs 23 Detecting presence of memory DIMMs 24 Programming timing parameters in the memory controller and the DIMMs 25 Configuring memory 26 Optimizing memory settings 27 Initializing memory, such as ECC init 29 Memory testing completed PCI Bus 50 Enumerating PCI busses 51 Allocating resources to PCI bus 52 Hot Plug PCI controller initialization 53 – 57 Reserved for PCI Bus USB 58 Resetting USB bus 59 Reserved for USB ATA/ATAPI/SATA 5A Resetting PATA/SATA bus and all devices 5B Reserved for ATA SMBus 5C Resetting SMBus 5D Reserved for SMBus Local Console 70 Resetting the VGA controller 71 Disabling the VGA controller 72 Enabling the VGA controller Remote Console 78 Resetting the console controller 79 Disabling the console controller 7A Enabling the console controller continued Error Messages and Beep Codes Table 41. Port 80h POST Codes (continued) POST Code Description of POST Operation Keyboard (USB) 90 Resetting keyboard 91 Disabling keyboard 92 Detecting presence of keyboard 93 Enabling the keyboard 94 Clearing keyboard input buffer 95 Instructing keyboard controller to run Self Test (PS/2 only) Mouse (USB) 98 Resetting mouse 99 Disabling mouse 9A Detecting presence of mouse 9B Enabling mouse Fixed Media B0 Resetting fixed media B1 Disabling fixed media B2 Detecting presence of a fixed media (hard drive detection etc.) B3 Enabling/configuring a fixed media Removable Media B8 Resetting removable media B9 Disabling removable media BA Detecting presence of a removable media (CD-ROM detection, etc.) BC Enabling/configuring a removable media BDS Dy Trying boot selection y (y=0 to 15) PEI Core E0 Started dispatching PEIMs (emitted on first report of EFI_SW_PC_INIT_BEGIN EFI_SW_PEI_PC_HANDOFF_TO_NEXT) E2 Permanent memory found E1, E3 Reserved for PEI/PEIMs DXE Core E4 Entered DXE phase E5 Started dispatching drivers E6 Started connecting drivers continued Intel Desktop Board DH55TC Technical Product Specification Table 41. Port 80h POST Codes (continued) POST Code Description of POST Operation DXE Drivers E7 Waiting for user input E8 Checking password E9 Entering BIOS setup EB Calling Legacy Option ROMs Runtime Phase/EFI OS Boot F4 Entering Sleep state F5 Exiting Sleep state F8 EFI boot service ExitBootServices ( ) has been called F9 EFI runtime service SetVirtualAddressMap ( ) has been called FA EFI runtime service ResetSystem ( ) has been called PEIMs/Recovery 30 Crisis Recovery has initiated per user request 31 Crisis Recovery has initiated by software (corrupt flash) 34 Loading recovery capsule 35 Handing off control to the recovery capsule 3F Unable to recover Error Messages and Beep Codes Table 42. Typical Port 80h POST Sequence POST Code ...