Évaluations - 2, GPA: 3.5
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Facilité d'utilisation
In Motorola multiplexed-bus mode this pin is DS, an active high input which works with CS to enable read and write operation. In Intel/ National multiplexed-bus mode this pin is RD, an active low input which enables a read-cycle and configures the data bus lines (AD0-AD7) as outputs. 4 44 AS/ALE Address Strobe / Address Latch Enable (Input). Falling edge is used to sample address into the Address Latch circuit. 5 45 CS Chip Select (Input). Active low input enabling a microprocessor read or write of control or status registers. 6 46 DTA Data Acknowledgment (Active Low Output). Indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then tri-states, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level when the pin is tri-stated. Note that CPU read/writes from/to the Data and Connection memories occur on the serial or parallel port clock edges, and DTA will not change state if the clock is halted. 7 47 IRQ Interrupt Request (Active High Output). Output indicates that the MT90840 has detected an alarm condition. The indication of the specific condition can be read in the ALS (Alarm Status) Register. The CPU should read ALS, identify the source for the interrupt and then rewrite the mask bits to re-enable the IRQ signal. 8 48 RES RESET (Schmitt Input). Asynchronous device reset. A logic-high signal should be applied during power-up to bring the MT90840 internal circuitry to a defined state. Serial and parallel TDM outputs (STo0-7, STi0-7, and PDo0-7) are held in high-impedance state after reset until programmed otherwise. This input must be held low during normal operation. 9 49 IC Internal Connection. The user must connect this pin to VSS. This pin must remain low for the MT90840 to function normally, and to comply with IEEE 1149 (JTAG) boundary scan requirements. This pin is pulled low internally when not driven. 10, 26, 27 1-4, 27-31 50-54 76-80 NC No Connection. 13-20 57-64 STi0-STi7 Serial Inputs 0 to 7 (Bidirectional). Serial TDM data-streams at 2.048, 4.096 or 8.192 Mbps, with 32, 64 or 128 channels respectively per stream. For 2.048 and 4.096 Mbps applications, streams STi0-STi7 can be used, while for 8.192 Mbps, only streams STi0-STi3 are used (512 channel limit). These eight bidirectional lines can be programmed as inputs (default) or outputs on a per-channel basis. 21 65 C4/8R1 Serial Clock Reference Input 1. When enabled by the C4/8R bit (high) in the TIM Register, this input receives the 4.096 or 8.192 MHz serial port clock reference. If the C4/8R bit is set low, or if the INTCLK bit is set high, this input is ignored by the MT90840. In Timing Mode 1 (TM1), or at 8.192 MHz, the C4/8 input is used directly to shift data in and out of the serial port. In Timing Mode 2 (TM2) at 4.096 MHz, the C4 input from an external clock source (e.g. a PLL locked to an 8 kHz reference) is phase-corrected by the MT90840, and used to generate the serial port SPCKo and F0 outputs. In Timing Modes 3 and 4 (TM3 and TM4) this input is not used. For more details on the use of this signal, see the description of Timing Mode 1 and Timing Mode 2. MT90840 Preliminary Information Pin Description (continued) Pin # Name Description84 100 22 66 F0i/o Serial Port Frame Synchronization (Bidirectional). This 8 kHz frame pulse signal indicates the TDM 125 msec frame boundary on the serial data port. This pin is compatible with both ST-BUS/MVIP and GCI formatted framing signals. In TM1 this pin is an input, and the MT90840 senses the polarity of this frame pulse and automatically adapts the serial data port timing to the applicable format (ST-BUS or GCI). In TM2 with SFDI =1 this signal is an input, and its expected format is determined by the SPFP bit in the GPM Register. In TM2 (with SFDI =0), and in TM3, this signal is an output, generated from the internal timing and synchronized to the SPCKo output clock. The polarity of the F0 pulse is determined by the SPFP bit in the GPM Register. In TM4 this pin is not used. 23 67 C4/8R2 C4/8R2 Serial Clock Reference Input 2. When enabled by the C4/8R bit (low) in the TIM Register, this input receives the 4.096 or 8.192 MHz serial port clock reference. If the C4/8R bit is set high, or if the INTCLK bit is set high, this input is ignored by the MT90840. (See pin description for C4/8R1.) 28-31 70-73 CTo3CTo0 External Control Lines 3 to 0 (Output). Output signals generated from the MT90840 Transmit Path Connection Memory (TPCM). The four serial CTo output lines represent the contents of the four CT bits in the TPCM, and are clocked at the parallel port rate (up to 19.44 MHz). See Per-Channel Functions section. 34-41 81-88 PDo7-PDo 0 Parallel Data Output Port 7 to 0 (Output). These eight outputs carry the parallel port data bytes in the transmit direction and operate at data rates up to 19.44 Mbyte/s. 42 89 PPFTi/o Parallel Port Framing, Transmit (Bidirectional). This signal delineates the start...