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A UART break-detect reset (P89LPC903) will have the same effect as a non-zero Status Bit. RPE (UCFG1.6) RST Pin WDTE (UCFG1.7) Watchdog Timer Reset Software Reset SRST (AUXR1.3) Chip Reset Power-on Detect UART Break Detect EBRR (AUXR1.6) Brownout Detect Reset BOPD (PCON.5) Figure 9-1: Block Diagram of Reset 2003 Dec 8 73 Philips Semiconductors User’s Manual - Preliminary RESET P89LPC901/902/903 RSTSRC Address: DFH Not bit addressable 7 6 5 4 3 2 1 0 --BOF POF R_BK R_WD R_SF R_EX Reset Sources: Power-on only Reset Value: xx110000B (This is the power-on reset value. Other reset sources will set corresponding bits.) BIT SYMBOL FUNCTION RSTSRC.7-6 -Reserved for future use. Should not be set to 1 by user programs. RSTSRC.5 BOF Brownout Detect Flag. When Brownout Detect is activated, this bit is set. It will remain set until cleared by software by writing a ’0’ to the bit. (Note: On a Power-on reset, both POF and this bit will be set while the other flag bits are cleared.) RSTSRC.4 POF Power-on Detect Flag. When Power-on Detect is activated, the POF flag is set to indicate an initial power-up condition. The POF flag will remain set until cleared by software by writing a ’0’ to the bit.. (Note: On a Power-on reset, both BOF and this bit will be set while the other flag bits are cleared.) RSTSRC.3 R_BK Break detect reset. If a break detect occurs and EBRR (AUXR1.6) is set to ’1’, a system reset will occur. This bit is set to indicate that the system reset is caused by a break detect. Cleared by software by writing a ’0’ to the bit or on a Power-on reset. RSTSRC.2 R_WD Watchdog Timer reset flag. Cleared by software by writing a ’0’ to the bit or a Power-on reset.(NOTE: UCFG1.7 must be = 1). RSTSRC.1 R_SF Software reset Flag. Cleared by software by writing a ’0’ to the bit or a Power-on reset. RSTSRC.0 R_EX External reset Flag. When this bit is ’1’, it indicates external pin reset. Cleared by software by writing a ’0’ to the bit or a Power-on reset. If RST is still asserted after the Power-on reset is over, R_EX will be set. Figure 9-2: Reset Sources Register 2003 Dec 8 74 Philips Semiconductors User’s Manual - Preliminary ANALOG COMPARATORS P89LPC901/902/903 10. ANALOG COMPARATORS One analog comparator is provided on the P89LPC901 and two analog comparators are provided on both the P89LPC902 and P89LPC903 . Comparator operation is such that the output is a logical one when the positive input is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. The output may be read in a register. On the P89LPC902 the output may also be routed to a pin. The comparator(s) may be configured to cause an interrupt when the output value changes. The connections to the comparator(s) are shown in Figure 10-2 - Figure 10-4. The comparator functions to VDD = 2.4V. When the comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds. The comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service. Comparator Configuration The comparator(s) have a control register(s), CMPn, and is shown in Figure 10-1. The possible configurations for the comparator are shown in Figure 10-5. CMPn Address: ACh Not bit addressable Reset Source(s): Any reset 7 6 5 4 3 2 1 0 --CEn -CNn OEn COn CMFn Reset Value: xx000000B BIT SYMBOL FUNCTION CMP.7, 6 -Reserved for future use. CMP.5 CEn Comparator enable. When set, the comparator function is enabled. Comparator output is stable 10 microseconds after CEn is set. CMP.4 -Reserved for future use. CMP.3 CNn Comparator negative input select. When 0, the comparator reference pin CMPREF is selected as the negative comparator input. When 1, the internal comparator reference, Vref, is selected as the negative comparator input. CMP.2 OEn Output enable. When 1, the comparator output is connected to the CMPn pin if the comparator is enabled (CEn = 1). This output is asynchronous to the CPU clock. CMP.1 COn Comparator output, synchronized to the CPU clock to allow reading by software. CMP.0 CMFn Comparator interrupt flag. This bit is set by hardware whenever the comparator output COn changes state. This bit will cause a hardware interrupt if enabled. Cleared by software. Figure 10-1: Comparator Control Registers (CMP1 and CMP2) 2003 Dec 8 75 Philips Semiconductors User’s Manual - Preliminary ANALOG COMPARATORS P89LPC901/902/903 + - CIN1A Comparator (P0.5) CMPREF Vref CN1 Change Detect CMF1 Interrupt EC CO1 Figure 10-2: Comparator Input and Output Connections - P89LPC901 + - (P0.4) CIN1A Comparator 1 CO1 OE1 (P0.5) CMPREF Vref + - (P0.2) CIN2A Comparator 2 CO2 OE2 CN1 CMP2 (P0.0) CMP1 (P0.6) Change Detect CMF1 Change Detect CMF2 Interrupt CN2 EC Figure 10-3: Comparator Input and Output Connections - P89LPC902 2003 Dec 8 76 Philips Semiconductors User’s Manual - Prelimi...

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