Therefore, try as much as possible to apply the voltage level close to VDD or GND. (4) Handling of unused pins Since the input impedance of the input pins is extremely high, operating the device with these pins in the open circuit state can lead to unstable voltage level and malfunctions due to noise. Therefore, pull- up or pull-down resistors should be provided for all unused input pins. 12-2. Notes on packaging (1) Soldering heat resistance. If the temperature within the package exceeds 260, t

4) If data is required in less than 52 clock pulses, that part of the data can be gotten by setting the CE pin low after the necessary number of clock pulses have been output. Example: If only the data from “seconds” to “day of the week” is needed: After 28 clock pulses, set the CE pin low in order to get the data from “seconds” to “day of the week.” 5) When performing successive data read operations, a wait (tRCV) is necessary after the CE pin is set low. 6) Note that if an update operation (a

Epson IS energy savings. NOTICE • The material is subject to change without notice. • Any part of this material may not be reproduced or duplicated in any form or any means without the written permission of Seiko Epson. • The information, applied circuit, program, using way etc., written in this material is just for reference. Seiko Epson does not assume any liability for the occurrence of infringing any patent or copyright of third party. This material does not authorize the licence for any pat

Max. Unit CS1 set-up time tSU(CS1) 1000 Address set-up time before ALE tSU(A-ALE) 50 Address hold time after ALE th(ALE-A) 50 ALE pulse width tw(ALE) 80 ALE set-up time before read tSU(ALE-R) 0 ns ALE set-up time after read tSU(R-ALE) 50 Data output transfer time after read tPZV(R-Q) CL=150 pF 120 Data output floating transfer time after read tPVZ(R-Q) 0 70 CS1 hold time th(CS1) 1000 Read recovery time trec(W) 200 (1) Write mode VIH2 tsu(CS1) tsu(A-ALE) tw(ALE) th(ALE-A) tsu(ALE-W) tw(W) VIH1 VI

When the HOLD bits is 1 and the BUSY bit is 0, read and write are enabled. When the HOLD bit is 1, any incrementation in the count is held within the RTC. The held incrementation is automatically compensated for when the HOLD bit becomes 0. (Second and subsequent incrementations are ignored.) Therefore, if the HOLD bit is at 1 for two or more seconds in succession, the time will be slightly slow (delay). Make sure that any access to the S1 to W registers is completed within one second, then clea

3. Write to 30-second ADJ bit The 30-seconds ADJ function is enabled by writing 1 to the 30-seconds ADJ bit. Note that the counter registers (S1 to W) cannot be accessed for 76.3 .s after this write. Therefore, follow one of the procedures shown below to use this function. START END 30 s ADJ bit < 1 Read the 30 s ADJ bit Wait 76.3 .s NO YES 30 s ADJ bit=0? or START END 30 s ADJ bit < 1 Read the 30 s ADJ bit NO YES 30 s ADJ bit=0? Note The crystal unit could be damaged if subjected to excessive s

(10) Changing the TE bit value from "1" to 0" stops the fixed-cycle timer's function (stops the countdown). Page . 24 ETM12E-01 RX . 8564 LC 13.3. Alarm Interrupt Function The alarm interrupt generation function generates interrupt events for alarm settings such as date, day, hour, and minute settings. When an interrupt event occurs, the AF bit value is set to "1" and the /INT pin goes to low level to indicate that an event has occurred. . When an alarm interrupt event occurs, low-level output f

AC Characteristics GND = 0 V , VDD=1.8Vto5.5V,Ta= .40 °C to +85 °C Item Symbol Condition Min. Typ. Max. Unit SCL clock frequency fSCL 400 kHz Start condition setup time tSU;STA 0.6 .s Start condition hold time tHD;STA 0.6 .s Data setup time tSU;DAT 100 ns Data hold time tHD;DAT 0 ns Stop condition setup time tSU;STO 0.6 .s Bus idle time between start condition and stop condition tBUF 1.3 .s Time when SCL = "L" tLOW 1.3 .s Time when SCL = "H" tHIGH 0.6 .s Rise time for SCL and SDA tr 0.3 .s Fall

Once this flag bit's value is "1", its value is retained until a "0" is written to it. . For details, see "8.3. Fixed-cycle Timer Interrupt Function". 3) AF (Alarm Flag) bit If set to "0" beforehand, this flag bit's value changes from "0" to 1" when an alarm interrupt event has occurred. Once this flag bit's value is "1", its value is retained until a "0" is written to it. . For details, see "8.5. Alarm Interrupt Function". 4) VLF (Voltage Low Flag) bit This flag bit indicates the retained statu

. Before entering settings for operations, we recommend writing a "0" to the AIE bit to prevent hardware interrupts from occurring inadvertently while entering settings. . When the STOP bit or RESET bit value is "1" alarm interrupt events do not occur. . When the alarm interrupt function is not being used, the Alarm registers (Reg - 8 to A) can be used as a RAM register. In such cases, be sure to write "0" to the AIE bit. . When the AIE bit value is "1" and the Alarm registers (Reg - 8 to A) is