
SRAM uses rising edges only ¦ Echo clocks (CQ and CQ) simplify data capture in high speed systems ¦ Data valid pin (QVLD) to indicate valid data on the output ¦ Synchronous internally self-timed writes [1] ¦ Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD ¦ HSTL inputs and variable drive HSTL output buffers ¦ Available in 165-ball FBGA package (15 x 17 x 1.4 mm) ¦ Offered in both in Pb-free and non Pb-free packages ¦ JTAG 1149.1 compatible test access port ¦ Delay Lock Loop (DLL) for accurate data